PUBLICATION
Books and Book Chapters
1. Ming-Jer Chen and Ming-Pei Lu, Probing Atomic-sized Oxide Traps, Encyclopedia of Nanoscience and Nanotechnology, American Scientific Publishers, 2010.
Referred Papers
1. M. J. Chen and C. Y. Wu, “A new method for computer-aided optimization of solar cell structures,” Solid-State Electronics, vol. 28, pp. 751-761, 1985. [link]
2. M. J. Chen and C. Y. Wu, “A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in hold current prediction,” Solid-State Electronics, vol. 28, pp. 855-866, 1985. [link]
3. M. J. Chen and C. Y. Wu, “A new analytical 3-dimensional model for substrate resistance in CMOS latchup structures,” IEEE Trans. Electron Devices, vol. 33, pp. 489-493, April 1986. [link]
4. M. J. Chen and C. Y. Wu, “An efficient two-dimensional model for CMOS latchup analysis,” Solid-State Electronics, vol. 29, pp. 395-407, April 1986. [link]
5. M. J. Chen and C. Y. Wu, “An efficient method for calculating the dc triggering currents in CMOS latch-up,” Solid-State Electronics, vol. 29, pp. 551-554, May 1986. [link]
6. M. J. Chen and C. Y. Wu, “Correlations between CMOS latch-up characteristics and substrate structure parameters,” Solid-State Electronics, vol. 29, pp. 1079-1086, Oct. 1986. [link]
7. M. J. Chen, S. C. Sze, H. H. Chen, and C. Y. Wu, “A new structure-oriented model for well resistance in CMOS latch structures, “ IEEE Trans. Electron Devices, vol. 34, pp. 890-897, April 1987. [link]
8. M. J. Chen and C. Y. Wu, “A simplified computer analysis for normal-well guard ring efficiency in CMOS circuits,” Solid-State Electronics, vol. 30, pp. 879-882, Aug. 1987. [link]
9. M. J. Chen, “Effect of back-gate bias on tunneling leakage in a gated p+-n diode,” IEEE Electron Device Letters, vol. 12, pp. 249-251, May 1991. [link]
10. M. J. Chen, “New observation of gate current in off-state MOSFET,” IEEE Trans. Electron Devices, vol. 38, pp. 2118-2120, Sept. 1991. [link]
11. M. J. Chen, K. C. Chao, and T. H. Huang, ”Gate and drain currents in off-state buried-type p-channel LDD MOSFETs,” IEEE Electron Device Letters, vol. 13, pp. 654-657, Dec. 1992. [link]
12. M. J. Chen, et al., “A study of latch-up hysteresis in n-well CMOS by means of I-V characteristics and photoemission techniques,” Solid-State Electronics, vol. 36, pp. 539-545, April 1993. [link]
13. M. J. Chen, C. Y. Huang, and P. N. Tseng, “Analytical design formulation for minority-carrier well-type guard rings in CMOS circuits,” IEE Proceedings-G Circuits Devices and Systems, vol. 140, pp. 182-186, June 1993. [link]
14. M. J. Chen, et al., ”New observation of charge injection in MOS analog switches,” Electron Letters, vol. 30, pp. 213-214, Feb. 1994. [link]
15. M. J. Chen, K. C. Chao, et al., “New observation and the modeling of gate and drain currents in off-state p-MOSFETs,” IEEE Trans. Electron Devices, vol. 41, pp. 734-739, May 1994. [link]
16. C. Y. Huang and M. J. Chen, “Design model and guideline for n-well guard ring in epitaxial CMOS,” IEEE Trans. Electron Devices, vol. 41, pp. 1806-1810, Oct. 1994. [link]
17. K. C. Chao and M. J. Chen, “Fowler-Nordheim limited band-to-band tunneling (FNBB) for p-MOSFET gate current in a floating bulk condition, “ Solid-State Electronics, vol. 38, pp. 135-137, Jan. 1995. [link]
18. T. H. Huang and M. J. Chen, “Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure,” Solid-State Electronics, vol. 38, pp. 115-119, Jan. 1995. [link]
19. T. H. Huang, M. J. Chen, “Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar Transistors,” IEEE Trans. Electron Devices, vol. 42, pp. 321-327, Feb. 1995. [link]
20. M. J. Chen, Y. B. Gu, T. Wu, P. C. Hsu, T. H. Liu, “Weak inversion charge injection in analog MOS switches,” IEEE J. Solid-State Circuits, vol. 30, pp. 604-606, May 1995. [link]
21. Y. B. Gu, M. J. Chen, “A new quantitative model for weak inversion charge injection in MOSFET analog switches,” IEEE Trans. Electron Devices, vol. 43, pp. 295-302, Feb. 1996. [link]
22. M. J. Chen, J. S. Ho, T. H. Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling,” IEEE J. Solid-State Circuits, vol. 21, pp. 259-262, Feb. 1996. [link]
23. M. J. Chen, J. S. Ho, D. W. Chang, “Optimizing the match in weakly inverted MOSFETs by gated lateral bipolar action,” IEEE Trans. Electron Devices, vol. 43, pp. 766-773, May 1996. [link]
24. M. J. Chen, J. S. Ho, T. H. Huang, C. H. Yang, Y. N. Jou, T. Wu, “Back-gate forward bias method for low voltage CMOS digital circuits,” IEEE Trans. Electron Devices, vol. 43, pp. 904-910, June 1996. [link]
25. C. Y. Huang, M. J. Chen, J. K. Jeng, C. Y. Wu, “Low-temperature characteristics of well-type guard rings in epitaxial CMOS,” IEEE Trans. Electron Devices, vol. 43, pp. 2249-2260, Dec. 1996. [link]
26. M. J. Chen, J. S. Ho, “A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variations,” IEEE Trans. CAD of Integrated Circuits and Systems, vol. 16, pp. 343-352, April 1997. [link]
27. M. J. Chen, Y. B. Gu, W. C. Shen, T. Wu, P. C. Hsu, “A compact high-speed Miller-capacitance based sample-and-hold circuit,” IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, vol. 45, pp. 198-201, Feb. 1998. [link]
28. M. J. Chen, H. T. Huang, C. S. Hou, K. N. Yang, “Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFETs,” IEEE Electron Device Letters, vol. 19, pp. 134-136, April 1998. [link]
29. M. J. Chen, H. S. Lee, J. H. Chen, C. S. Hou, C. S. Lin, Y. N. Jou, “A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up,” IEEE Electron Device Letters, vol. 19, pp. 276-278, Aug., 1998. [link]
30. C. J. Chao, S. C. Wong, M. J. Chen, B. K. Liew, “An extraction method to determine interconnect parasitic parameters,” IEEE Trans. Semiconductor Manufacturing, vol. 11, pp. 615-623, Nov. 1998. [link]
31. M. J. Chen and C. S. Hou, “A novel cross-coupled inter-poly-oxide capacitor for mixed-mode CMOS process,” IEEE Electron Device Letters, vol. 20, pp. 360-362, July 1999. [link]
32. M. J. Chen, H. T. Huang, J. H. Chen, C. W. Su, C. S. Hou, and M. S. Liang, “Cell-based analytic statistical model with correlated parameters for intrinsic breakdown of ultrathin oxides,” IEEE Electron Device Letters, vol. 20, pp. 523-525, Oct. 1999. [link]
33. H. T. Huang, M. J. Chen, J. H. Chen, C. W. Su, C. S. Hou, and M. S. Liang, “Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown,” Japanese Journal of Applied Physics, vol. 39, p. 2026, April 2000. [link]
34. M. J. Chen, T. K. Kang, C. H. Liu, Y. J. Chang, and K. Y. Fu, “Oxide thinning percolation statistical model for soft breakdown in ultrathin gate oxides,” Applied Physics Letters, pp. 555-557, July 2000. [link]
35. M. J. Chen, T. K. Kang, C. H. Liu, Y. J. Chang, and K. Y. Fu, “Forward gated-diode measurement of filled traps in high-field stressed thin oxides,” IEEE Trans. Electron Devices, pp. 1682-1683, Aug. 2000. [link]
36. K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M. Lin, M. H. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+ poly-gate pMOSFETs with ultrathin gate oxides,” IEEE Trans. Electron Devices, pp. 2161-2166, Nov. 2000. [link]
37. M. J. Chen, T. K. Kang, Y. H. Lee, C. H. Liu, Y. J. Chang, and K. Y. Fu, “Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdown,” Journal of Applied Physics, pp. 648-653, Jan. 2001. [link]
38. K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. H. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs,” IEEE Trans. Electron Devices, pp.1159-1164, June 2001. [link]
39. M. J. Chen, H. S. Lee, and S. T. Chen, “Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I-V characteristics in NMOS devices,” IEEE Trans. Electron Devices, pp.1237-1244, June 2001. [link]
40. H. T. Huang, M. J. Chen, et al., “ A trap generation closed-form statistical model for intrinsic oxide breakdown,” IEEE Trans. Electron Devices, pp. 1275-1277, June 2001. [link]
41. K. Y. Chou and M. J. Chen, ”ESD protection under grounded-up bond pads in 0.13-um eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology,” IEEE Electron Device Letters, vol.22, pp. 342-344, July 2001. [link]
42. K. Y. Chou and M. J. Chen, ”Active circuits under wire bonding I/O pads in 0.13um eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology,” IEEE Electron Device Letters, vol.22, pp.466-468, Oct. 2001. [link]
43. T. K. Kang, M. J. Chen, et al., “Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism,” IEEE Trans. Electron Devices, pp. 2317-2322, Oct. 2001. [link]
44. K.N. Yang, H.T. Huang, M. J. Chen, et al,” Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs,” IEEE Trans. Electron Devices, vol. 48, pp.2790-2795, Dec. 2001. [link]
45. C. J. Chao, M. J. Chen, et al., “Characterization and modeling of on-chip spiral inductors for Si RF IC’s,” IEEE Trans. Semiconductor Manufacturing, pp. 19-29, Feb. 2002. [link]
46. Caleb Y. S. Cho, M. J. Chen, J. H. Lin, and C. F. Chen, “A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells,” IEEE Electron Device Letters, vol. 23, pp. 422-424, July 2002. [link]
47. K. Y. Chou, M. J. Chen, C. W. Liu, and B. H. Lin, “Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure,” IEEE Trans. Device and Materials Reliability, pp. 50-59, September 2002. [link]
48. M. J. Chen and M. P. Lu, “On-off switching of edge direct tunneling currents in metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, pp. 3488-3490, October 2002. [link]
49. K. Y. Chou, M. J. Chen, and C. W. Liu, “Active Devices under CMOS I/O Pads,” IEEE Trans. Electron Devices, pp. 2279-2287, December 2002. [link]
50. Caleb Y. S. Cho and M. J. Chen, “Forward bias enhanced channel hot electron injection for low-level programming improvement in multilevel flash memory,” IEICE Trans. ELECTRON, Vol. E87-E, pp.1204-1207, July 2004. [link]
51. Caleb Y. S. Cho and M. J. Chen, “Improved subthreshold slope method for extracting gate capacitive coupling coefficient in Flash memory cell, “ Solid-State Electronics, pp. 1189-1195, July 2004. [link]
52. T. K. Kang, K. C. Su, Y. J. Chang, M. J. Chen, and S. H. Yen, “Edge quantum yield in n-channel metal-oxide-semiconductor field-effect transistor,” Journal of Applied Physics, vol. 96, pp. 1743-1744, Aug. 2004. [link]
53. M. J. Chen, H. T. Huang, Y. C. Chou, R. T. Chen, Y. T. Tseng, P. N. Chen, and C. H. Diaz, “Separation of Channel Backscattering Coefficients in Nanoscale MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp.1409-1415, September 2004. [link]
54. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005. [link]
55. M. P. Lu and M. J. Chen, “Oxide-trap-enhanced Coulomb energy in a metal-oxide-semiconductor system”, Physical Review B, vol. 72, pp. 235417-1—235417-5, December 2005. [link]
56. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J. Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Applied Physics Letters, vol. 88, pp. 053114-1—053114-3, Feb. 2006. [link]
57. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J. Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Selected Articles in Virtual Journal of Nanoscale Science & Technology, Vol. 13, Issue 6, 2006. [link]
58. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J. Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Selected Articles in Virtual Journal of Biological Physics Research, Vol. 11, Issue 4, 2006. [link]
59. M. P. Lu, W. C. Lee, M. J. Chen, “Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors,” Applied Physics Letters, vol. 88, pp. 063511-1—063511-3, Feb. 2006. [link]
60. C. Y. S. Cho, M. J. Chen, C. F. Chen, P. Tuntasood, D. T. Fan, and T. Y. Liu, “A novel self-aligned highly reliable sidewall split-gate Flash memory,” IEEE Trans. Electron Devices, vol. 53, pp. 465-473, March 2006. [link]
61. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, M. J. Chen, S. Liu, and C. H. Diaz, “Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependence diffusion model,” Japanese Journal of Applied Physics, vol. 45, pp. L849-L851, August 2006. [link]
62. Y. M. Sheu, K. W. Su, S. Tian, S. J. Yang, C. C. Wang, M. J. Chen, and S. Liu, “Modeling the well-edge proximity effect in highly-scaled MOSFETs,” IEEE Trans. Electron Devices, Vol. 53, pp. 2792-2798, Nov., 2006. [link]
63. M. J. Chen and Y. M. Sheu, “Effect of uniaxial strain on anisotropic diffusion in silicon,” Applied Physics Letters, Vol. 89, pp. 161908-1-181908-3, Oct., 2006. [link]
64. M. J. Chen, S. G. Yan, R. T. Chen, C. Y. Hsieh, P. W. Huang, and H. P. Chen, “Temperature oriented experiment and simulation as corroborating evidence of MOSFET backscattering theory,” IEEE Electron Device Letters, vol. 28, pp. 177-179, Feb. 2007. [link]
65. C. Y. Hsieh and M. J. Chen, “Measurement of channel stress using gate direct tunneling current in uniaxially stressed n-MOSFETs,” IEEE Electron Device Letters, vol. 28, pp. 818-820, Sept. 2007. [link]
66. D. W. Lin, M. L. Cheng, S. W. Wang, C. C. Wu, and M. J. Chen, “A constant mobility method to enable MOSFET series resistance extraction,” IEEE Electron Device Letters, vol. 28, pp. 1132-2234, December, 2007. [link]
67. M. J. Chen, C. C. Lee, and M. P. Lu, “Probing a nonuniform two-dimensional electron gas with random telegraph signals,” Journal of Applied Physics, vol. 103, p. 034511, Feb. 2008. [link]
68. C. Y. Hsieh and M. J. Chen, “Electrical measurement of local stress and lateral diffusion near source/drain extension corner of uniaxially stressed n-MOSFETs,” IEEE Trans. Electron Devices, vol.55, pp. 844-849, March 2008. [link]
69. M. J. Chen and L. F. Lu, “A parabolic potential barrier oriented compact model for the kBT layer’s width in nano-MOSFETs,” IEEE Trans. Electron Devices, vol.55, pp. 1265-1268, May 2008. [link]
70. D. W. Lin, M. Wang, M. L. Cheng, Y. M. Sheu, B. Tarng, C. M. Chu, C. W. Nieh, C. P. Lo, W. C. Tsai, R. Lin, S. W. Wang, K. L. Cheng, C. M. Wu, M. T. Lei, C. C. Wu, C. H. Diaz, and M. J. Chen, “A millisecond-anneal-assisted selective (FUSI) gate process,” IEEE Electron Device Letters, vol. 29, pp. 998-1000, Sept. 2008. [link]
71. M. J. Chen, L. F. Lu, and C. Y. Hsu, “On the mean-free-path for backscattering in kBT layer of bulk nano-MOSFETs,” IEEE Trans. Electron Devices, vol. 55, pp. 3594-3598, Dec. 2008. [link]
72. C. Y. Hsieh, Y. T. Lin, and M. J. Chen, “Distinguishing between STI stress and delta width in gate direct tunneling current of narrow n-MOSFETs,” IEEE Electron Device Letters, vol. 30, pp. 529-531, May. 2009. [link]
73. M. Y. Lu, M. P. Lu, Y. A. Chung, M. J. Chen, Z. L. Wang, and L. J. Chen, “Intercrossed sheet-like Ga-doped ZNS nanostructures with superb photocatalytic activity and photoresponse,” Journal of Physical Chemistry C, vol. 113, pp. 12878-12882, July 2009. [link]
74. C. Y. Hsu, C. C. Lee, Y. T. Lin, C. Y. Hsieh, and M. J. Chen, “Enhanced hole gate direct tunneling current in process-induced uniaxial compressive stress p-MOSFETs,” IEEE Trans. Electron Devices, vol. 56, pp. 1667-1673, August 2009. [link]
75. D. W. Lin, M. L. Cheng, S. W. Wang, C. C. Wu, and M. J. Chen, “A novel method of MOSFET series resistance extraction featuring constant mobility criteria and mobility universality,” IEEE Trans. Electron Devices, vol. 57, pp. 890-897, April 2010. [link]
76. D. W. Lin, C. L. Chen, and C. C. Wu, "An extreme surface proximity-push for embedded-SiGe in pMOSFETs featuring self-aligned silicon-reflow (SASR)," IEEE Electron Devices Letters,vol.31, pp.924-926, Sept. 2010. [link]
77. W. H. Lee and M. J. Chen, "Gate direct tunneling current in uniaxially compressive strained nMOSFETs: A sensitive measure of electron piezo effective mass," IEEE Trans. Electron Devices, vol. 58, pp. 39-45, Jan. 2011. [link]
78. M. J. Chen, C. C. Lee, and K. H. Cheng, "Hole effective masses as a booster of self-consistent six-band k‧p simulation in inversion layers of pMOSFETs," IEEE Trans. Electron Devices, vol. 58, pp.931-937, April 2011. [link]
79. C. Y. Hsu, H. G. Chang, and M. J. Chen, "A method of extracting metal-gate high-k material parameters featuring electron gate tunneling transition," IEEE Trans. Electron Devices, vol. 58, pp. 953-959, April 2011. [link]
80. M. J. Chen, S. C. Chang, S. J. Kuang, C. C. Lee, W. H. Lee, K. H. Cheng, and Y. H. Zhan, "Temperature-dependent remote-Coulomb-limited electron mobility in n+ polysilicon ultrathin gate oxide nMOSFETs," IEEE Trans. Electron Devices, vol. 58, pp. 1038-1044, April 2011. [link]
81. M. J. Chen and C. Y. Hsu, "Evidence for a very small tunneling effective mass (0.03 mo) in MOSFET high-k (HfSiON) gate dielectrics," IEEE Electron Device Letters, vol. 33, pp. 468-470, April 2012. [link]
82. M. J. Chen, L. M. Chang, S. J. Kuang, C. W. Lee, S. H. Hsieh, C. A. Wang, S. C. Chang, and C. C. Lee, "Temperature -oriented mobility measurement and simulation to assess surface roughness in ultrathin-gate-oxide (~1 nm) nMOSFETs and Its TEM evidence," IEEE Trans. Electron Devices, vol. 59, pp. 949-955, April 2012. [link]
83. M. J. Chen and W. H. Lee, "Evidence for the fourfold-valley confinement electron piezo-effective-mass coefficient in Inversion layers of <110> uniaxial tensile strained (001) nMOSFETs," IEEE Electron Device Letters, vol. 33, pp. 755-757, June 2012. [link]
84. M. J. Chen, W. H. Lee, and Y. H. Huang," Error-free Matthiessen’s rule in the MOSFET universal mobility region," IEEE Trans. Electron Devices, vol. 60, pp. 753-758, Feb. 2013. [link]
85. M. J. Chen, C. C. Lee, and W. L. Chen, "Effect of strained kp deformation potentials on hole inversion-layer mobility ," IEEE Trans. Electron Devices, vol. 60, pp. 1365-1371, April 2013. [link]
86. M. J. Chen, L. M. Chang, S. Y. Wei, W. L. Chen, T. H. Yeh, C. L. Chen, and Y. C. Liao, "Probing long-range Coulomb interactions in nanoscale MOSFETs," IEEE Electron Device Letters, vol. 34, no. 12, pp. 1563-1565, December 2013. [link]
87. M. J. Chen, C. L. Chen, S. H. Hsieh, and L. M. Chang," Plasmons-enhanced minority-carrier injection as a measure of potential fluctuations in heavily doped silicon," IEEE Electron Device Lett., vol. 35, no. 7, pp. 708-710, Jul. 2014. [link]
88. M. J. Chen, K. C. Tu, H. H. Wang, C. L. Chen, S. Y. Lai, and Y. S. Liu, "A statistical model for the headed and tail distributions of random telegraph signal magnitudes in nanoscale MOSFETs," IEEE Trans. Electron Devices, vol. 61, no. 7, pp. 2495-2502, July 2014. [link]
89. M. J. Chen, S. H. Hsieh, Y. C. Liao, C. L. Chen, and M. F. Tsai, "Criteria for plasmon-enhanced electron drag in Si metal-oxide-semiconductor devices," IEEE Electron Device Letters, vol. 36, no. 3, pp. 265-267, March 2015. [link]
90. M. J. Chen, K. C. Tu, L. Y. Chuang, and H. H. Wang, "Graphically transforming Mueller-Schulz percolation criteria to random telegraph signal magnitudes in scaled FETs," IEEE Electron Device Letters, vol. 36, no. 3, pp. 217-219, March 2015. [link]
91. M. J. Chen, S. H. Hsieh, and C. L. Chen, "Plasmon-enhanced phonon and ionized impurity scattering in doped silicon," Journal of Applied Physics, vol. 118, p. 045703, July 2015. [link]
Conference Papers
1. M. J. Chen and C. Y. Wu, “A general structure-oriented 2-D model for determining the substrate spreading resistance in bulk CMOS latch-up path and its application,” VLSI TSA, May 1985 (Taipei).
2. M. J. Chen, J. J. Kuo, P. N. Tseng, N. S. Tsai, and C. Y. Wu, “Photoemission identification of emitter resistance for CMOS latch-up hysteresis,” IEEE ICMTS, pp. 231-235, 1990 (Kyoto).
3. M. J. Chen, C. Y. Huang, P. N. Tseng, N. S. Tsai, and C. Y. Wu, “Design model for minority-carrier well-type guard rings in CMOS circuits,” IEEE CICC, 1991 (San Diego).
4. T. H. Huang, M. J. Chen, and C. Y. Wu, “Suppression of both sidewall injection and hot-carrier effects using laterally graded emitter in bipolar transistors,” VLSI TSA, pp. 205-209, 1991 (Taipei).
5. M. J. Chen, C. S. Hou, P. N. Tseng, R. Y. Shiue, H. S. Lee, J. H. Chen, “A compact model of holding voltage for latch-up in epitaxial CMOS,” IEEE IRPS, Proceedings, pp. 339-345, April 1997 (Denver).
6. C. J. Chao, S. C. Wong, M. J. Chen, B. K. Liew, “A New Method and Test Structure for Determination of Interconnect Parasitic Parameters,” Proceedings of the 28th European Solid-State Devices Research Conference (ESSDERC), pp. 644-647, September 1998.
7. H. T. Huang, M. J. Chen, J. H. Chen, C. W. Su, C. S. Hou, and M. S. Liang, “A trap generation statistical model in closed-form for intrinsic breakdown of ultrathin oxides,” IEEE Symposium on VLSI-TSA, Technical Digest, pp. 70-73, June 1999 (Taipei).
8. M. J. Chen and T. K. Kang, “Low-voltage forward gated diode: an early monitor of hot-carrier degradations in scaled MOSFETs,” IEEE IPFA Proceedings, pp. 195-199, July 1999 (Singapore).
9. H. T. Huang, M. J. Chen, J. H. Chen, C. W. Su, C. S. Hou, and M. S. Liang, “Monte Carlo sphere model for “effective oxide thinning” induced extrinsic breakdown,” SSDM, Extended Abstract, pp. 320-321, Sept. 1999 (Tokyo).
10. K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. H. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “Edge direct tunneling (EDT) induced drain and gate leakage in ultrathin gate oxide MOSFETs,” SSDM, Extended Abstracts, pp. 208-209, Aug. 2000 (Sendai).
11. H. T. Huang, M. J. Chen, “A novel sphere-based statistical model for local oxide thinning induced gate oxide breakdown,” SSDM, Extended Abstract, pp. 246-247, Aug. 2000 (Sendai).
12. K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. H. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp. 679-682, Dec. 2000 (San Francisco).
13. K.Y. Chou, M. J. Chen, et al., ”Die cracking evaluation and improvement in ULSI plastic package,” IEEE International Conference on Microelectronic Test Structures, March 2001(Kobe).
14. C. J. Chao, M. J. Chen, et al., “Characterization and modeling of on-chip inductor substrate coupling,” IEEE MTT Microwave Symposium Digest, pp. 157-160, April 2002.
15. C. J. Chao, M. J. Chen, et al., “Characterization and modeling of on-chip inductor substrate coupling,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 311-314, 2002 (Seattle).
16. M. J. Chen, H. T. Huang, K. C. Huang, P. N. Chen, C. S. Chang, and Carlos H. Diaz, “Temperature dependent channel backscattering coefficients in nanoscale MOSFETs,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp. 39-42, Dec. 2002 (San Francisco).
17. Y. M. Sheu, C. S. Chang, H. C. Lin, S. S. Lin, C. H. Lee, C. C. Wu, M. J. Chen, and C. H. Diaz, “Impact of STI Mechanical Stress in Highly Scaled MOSFETs,” IEEE Symposium on VLSI-TSA, Technical Digest, pp. 269-272, 2003 (Hsin-Chu).
18. Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz, “Study on STI Mechanical Stress Induced Variation in 90-nm CMOSFETs,” IEEE International Conference on Microelectronic Test Structures, pp. 205-208, March 2003 (Monterey).
19. Caleb Y. S. Cho, M. J. Chen, and C. F. Chen, “Fast and Precise Subthreshold Slope Method for Extracting Gate Capacitive Coupling Coefficient in Flash Memory Cells,” IEEE International Conference on Microelectronic Test Structures, pp. 186-190, March 2003 (Monterey).
20. C. S. Wang, M. J. Chen, W. C. Chang, W. S. Ke, C. F. Lee, K. C. Su, and E. N. Chou, “Plausible origin of electromigration lifetime extrapolation difference between wafer level isothermal test and package level constant current test,” IEEE IPFA Proceedings, pp. 169-172, July 2004 (Hsin-Chu).
21. C. S. Wang, W. C. Chang, W. S. Ke, C. F. Lee, K. C. Su, Y. J. Chang, E. N. Chou, and M. J. Chen, “Reliability control monitor guideline of negative bias temperature instability for 0.13 um CMOS technology,” IEEE IPFA Proceedings, pp. 315-318, July 2004 (Hsin-Chu).
22. M. P. Lu and M. J. Chen, “Anomalous Behaviors of Random Telegraph Signals in Ultra-thin Gate Oxide MOSFETs,” SSDM, Extended Abstracts, pp. 408-409, September 2004 (Tokyo).
23. M. J. Chen, R. T. Chen, and Y. S. Lin, “Decoupling channel backscattering coefficients in nanoscale MOSFETs to establish near-source channel conduction-band profiles,” IEEE Silicon Nanoelectronics Workshop, pp. 50-51, June 2005. (Kyoto).
24. C. S. Wang, W. C. Chang, W. S. Ke, C. T. Chiang, C. F. Lee, K. C. Sa, and M. J. Chen, “Characterization of embedded poly-heater pMOSFETs and its application on in-line wafer level NBTI monitor,” SSDM, Extended Abstracts, September 2005 (Kobe).
25. Ming-Yen Lu, Ming-Pei Lu, Ming-Jer Chen and Lih-Juann Chen “The Photoconductivity of Ga:ZnS Nanowalls,” 212th ECS Meeting, 2007.
26. C. Y. Hsieh, Y. T. Lin, T. H. Liang, W. C. Lee, J. B. Bouche, and M. J. Chen, “Effect of STI mechanical stress on p-channel gate oxide integrity,” IEEE Semiconductor Interface Specialist Conference, p.5, 2007 (Arlington).
27. M. J. Chen, “NanoFET channel backscattering: Recent research trends and challenging issues,” IEDMS, (Invited), 2008 (Taichung).
28. C. Y. Hsu, H. G. Chang, S. J. Kuang, W. H. Lee, Y. C. Chen, C. C. Lee, and M. J. Chen, “Enhanced hole mobility in non-(001) oriented sidewall corner of Si pMOSFETs formed on (001) substrate,” IEEE Silicon Nanoelectronics Workshop, pp. 67-68, June 2010 (Honolulu).
29. K. C. Tu and M. J. Chen, “Random telegraph signals under External mechanical stress: A new method to probe trap structural relaxation in MOSFET Gate Dielectrics,” SSDM, September 2012 (Kyoto).
30. M. J. Chen (Invited Speaker), Long-Range Coulomb Interactions in Nanoscale MOSFETs: An Experimental Viewpoint, IEEE Simulation of Semiconductor Processes and Devices (SISPAD) workshop, (Yokohama, Japan), September 2014.
31. M. J. Chen (Invited Speaker), Plasmon Resonance as a key limiter in FETs scaling: Experimental Tasks, 2015 Osaka-NCTU Joint Workshop on Modeling and Simulation of Semiconductor Devices, (Hsin-Chu, Taiwan), May 2015.
32. S. H. Hsieh, J. C. Hung, H. J. Weng, M. F. Tsai, C. C. Chiang, and M. J. Chen, “Two Competing Limiters in MOSFETs Scaling: Neutral Defects and S/D Plasmons,” in IEEE Silicon Nanoelectronics Workshop, (Honolulu, USA), pp. 32-33, June 2016.
33. S. H. Hsieh, J. C. Hung, and M. J. Chen, “A new microscopic formalism for the electron scattering by “paired” dipoles in HKMG MOSFETs,” IEEE Simulation of Semiconductor Processes and Devices (SISPAD), (Nuremberg, Germany), pp. 201-204, September 2016.
US Patents
PAT. NO. Title
1 6,992,929 Self-aligned split-gate NAND flash memory and fabrication process
2 6,222,221 Cross-coupled capacitors for improved voltage coefficient
3 6,072,677 Electrostatic discharge protective circuit formed by use of a silicon controlled rectifier
4 6,069,050 Cross-coupled capacitors for improved voltage coefficient
5 5,644,266 Dynamic threshold voltage scheme for low voltage CMOS inverter
6 5,594,683 SRAM cell using a CMOS compatible high gain gated lateral BJT
7 5,479,121 Compensating circuit for MOSFET analog switches
UB. APP. NO. Title
1 20060068529 Self-aligned split-gate NAND flash memory and fabrication process
2 20050207225 Self-aligned split-gate NAND flash memory and fabrication process